Unfortunately, this is exactly the correct workflow that we're stuck with for now. I have been building all of the devicetree blobs from scratch (essentially the last 2 steps of your process), but I can see some places that lend themselves well to automation, specifically the merge and build steps. Ultimately, we want to move to using devicetree overlays that will be loaded along with their corresponding bitstream which will keep the processing subsystem devicetree nodes/bindings independent of the nodes/bindings describing programmable logic devices. I will continue to look into a better methodology for generating and compiling devicetrees that (hopefully) doesn't require so many steps. Keep us updated on any snags or issues you may run into or any points that you think could be automated.
On Wednesday, July 20, 2016 at 12:59:54 PM UTC-7, Nick Burkitt wrote:
Here's the workflow I'm using. It works, but I don't like all the manual steps. Of course, once it's done it won't have to be repeated often.
- The first steps are prerequisites that may already exist (the last three are from my earlier Building the Kernel from Source post, and are needed only to get the devicetree compiler, dtc).
- The workflow closely follows this Xilinx Wiki page.
- If you
use the defaults for exporting the hardware and launching the SDK, <SDK workspace> will be a subdirectory of your Vivado project's *.sdk
directory.
- SNOODLE is an environment variable pointing to an arbitrary snickerdoodle project root.
Prerequisites
Workflow
|
Build project
|
Vivado: Generate
Block Design
|
|
Export hardware
|
Vivado Menu: File
> Export > Export Hardware
|
|
Open SDK
|
Vivado Menu: File
> Launch SDK
|
|
Add the BSP
repository in SDK
|
SDK Menu: Xilinx
Tools > Repositories > New
Select
folder device-tree-xlnx (see Prerequisites)
|
|
Create a Device
Tree Board Support Package
|
SDK Menu: File
> New > Board Support Package > Board Support Package OS:
device-tree > Finish
The .dts/.dtsi
files are now located in <SDK workspace>/device_tree_bsp_0/ folder (for
example).
|
|
Copy
zynq-snickerdoodle.dts to BSP folder
|
$ cd $SNOODLE
$ cp
u-boot-xlnx/arch/arm/dts/zynq-snickerdoodle.dts <SDK
workspace>/device_tree_bsp_0 (for example)
|
|
Merge DTS files
|
Copy any /include/
directives from system.dts to zynq-snickerdoodle.dts (e.g. pl.dtsi)
|
|
Build DTB
|
$ cd <SDK
workspace>/device_tree_bsp_0 (for example)
$ dtc -I dts -O
dtb -o devicetree.dtb zynq-snickerdoodle.dts
|
On Wednesday, July 20, 2016 at 9:44:51 AM UTC-7, Nick Burkitt wrote:
Hi Guys.
I'm using the Vivado project from our FPGA guy to produce a bitstream and devicetree BLOB for snickerdoodle. Following the workflow on
this wiki page, I end up with devicetree source that appears to match a generic Zynq 70xx, or possibly the Xilinx ZC702 development board, but not snickerdoodle. Specifically, it has entries for Ethernet, and two PS UARTs, but no WiLink8 SDIO WiFi module.
The Vivado "project device" is "snickerdoodle Development Platform (xc7z010clg400-1)." It's board rev 3.
Obviously I'm missing (or misapplying) some step along the way. What's the workflow/procedure for getting a devicetree that matches the snickerdoodle + Vivado PL hardware definition?
Thanks,
-Nick