I am having trouble getting the FCKL_CLK0 signal from the PS to the PL.
My configuration is as follows. I have a Snickerdoodle Prime board and I have install the Linux build from downloads center that was generated on Oct 21, 2018. I have install the board Vivado board files generated on April 23, 2018. In Vivado, I pulled a clock signal from FCLK_CLK0 from the PS in the block diagram and sent it to an output pin. Then in the .xdc file I assigned this signal to an IO pin. Checking this pin with an O-scope I don’t see anything. I have also generate an ILA to look at some signals that use the FCLK_CLK0 as there clock, Vivado then gives a warning that no clock was detected and that I should check the clock pins.
I have found some incomplete information in old posts that leads me to suspect that the linux build is turning of the output drivers from the FCLK_CLK0 on the PS side before the clock gets to the PL sides.
My first question is does my suspicion seem valid. My second question is, what is the simplest modification that I can make on the Linux side to enable this clock.
Thank you in advance for any insights that you can share with me.
Your workflow seems correct but can you confirm that your generated bitstream is being loaded properly? During the boot process, U-Boot will load a bitstream from the SD card and you will see the white (app) LED pulsing in a “breathing” pattern. You will also need to make sure you are providing a voltage reference for the I/O bank you are using for your output signal. Can you provide the constraints you’re using to route the FCLK0 to the output pin you are using?
I got this working, I will share my solution in case it helps other.
It appears that Linux turns on the FCLK drivers after loading the .bit file from the Linux side. I was loading a .bit file from the JTAG port which was leaving the clock off. My solution was to load a bit file from the linux side using the following command.
Then I loading the .bit file that I wanted to test along with its logic analyzer file through the JTAG port. I was then able to debug through the JTAG port.
Thank you for your comments Bush, and Lexus, they both helped me find my way to a solution.