Hi Arif, the Zynq chips on the snickerdoodle and snickerdoodle black do not include PCIe interfaces so that was not a consideration for the connectors.
However, the connectors are setup and routed for high speed signaling. For all differential capable pairs the target controlled impedance is 100 ohms and for single ended tracks 50 ohms.
The headers are appropriate for gigabit+ speed LVDS I/O per the manufacturer. The diff pairs have matched lengths in byte groups.
Please see the end of the schematic for detailed net length matching information: https://github.com/krtkl/open-source-schematics/blob/master/snickerdoodle/snickerdoodle-schematic-r3.pdf
On Monday, August 1, 2016 at 10:30:20 AM UTC-7, Arif Khan wrote:
Are these connectors and the routing to them optimized for high speed signalling? Can they handle say PCIE gen1/gen2 interfaces? Are the signal traces length matched from the ZYNQ FPGA to the these connectors? what is the impedance of these traces and are they setup for differential signaling.
Thanks.