Hardware Definition


Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick
I don't have the exact answer for you but I would think the Linux "device tree" database would be a starting point.

I would expect that the physical addresses of on-Zynq-chip peripherals are fixed and covered in the Xilinx manuals.

This might offer a starting point:

http://xillybus.com/tutorials/device-tree-zynq-1

On Wednesday, June 15, 2016 at 3:10:39 PM UTC-7, Nick Burkitt wrote:

Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick
Here's a link to the Zynq TRM: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

It may be overkill but if register mappings is what you want, you're probably not going to find them anywhere else. Register maps are going to be specific to specific peripherals/subsystems but Chapter 4 (page 113) should get you started.

On Wednesday, June 15, 2016 at 3:10:39 PM UTC-7, Nick Burkitt wrote:

Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick
I forgot I'm not dealing with a bare FPGA, and all the peripherals are on the chip. I've been too busy fighting the software battle to even look at the hardware. :-/ Of course if I had, the sight of an 1,800 page manual might have put me off my feed.
Okay, so UART0 is probably the USB console connection. And I guess that UART1 will need to be routed to some MIO connector or another.
Thanks!

-Nick

On Wednesday, June 15, 2016 at 5:07:07 PM UTC-7, Bush wrote:
Here's a link to the Zynq TRM: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

It may be overkill but if register mappings is what you want, you're probably not going to find them anywhere else. Register maps are going to be specific to specific peripherals/subsystems but Chapter 4 (page 113) should get you started.

On Wednesday, June 15, 2016 at 3:10:39 PM UTC-7, Nick Burkitt wrote:

Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick
The device tree may come into play in a different battle. We'll see...

On Wednesday, June 15, 2016 at 4:53:35 PM UTC-7, Rob Barris wrote:
I don't have the exact answer for you but I would think the Linux "device tree" database would be a starting point.

I would expect that the physical addresses of on-Zynq-chip peripherals are fixed and covered in the Xilinx manuals.

This might offer a starting point:


On Wednesday, June 15, 2016 at 3:10:39 PM UTC-7, Nick Burkitt wrote:

Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick
Yes, UART0 is (by default) bridged with the platform controller USB device interface to provide the Linux console. You can set UART1 on the MIO pins that are connected to J3. You will need to be aware that the pins on J3 are +1.8V standard, so you'll need to be careful what you connect to them.

On Wednesday, June 15, 2016 at 6:48:40 PM UTC-7, Nick Burkitt wrote:
I forgot I'm not dealing with a bare FPGA, and all the peripherals are on the chip. I've been too busy fighting the software battle to even look at the hardware. :-/ Of course if I had, the sight of an 1,800 page manual might have put me off my feed.
Okay, so UART0 is probably the USB console connection. And I guess that UART1 will need to be routed to some MIO connector or another.
Thanks!

-Nick

On Wednesday, June 15, 2016 at 5:07:07 PM UTC-7, Bush wrote:
Here's a link to the Zynq TRM: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

It may be overkill but if register mappings is what you want, you're probably not going to find them anywhere else. Register maps are going to be specific to specific peripherals/subsystems but Chapter 4 (page 113) should get you started.

On Wednesday, June 15, 2016 at 3:10:39 PM UTC-7, Nick Burkitt wrote:

Hi Guys.

Where can I find the snickerdoodle memory and device register map?
Thanks,

-Nick