HDMI ..Ax..VDMA..PL/PS ddr partitioning.

snickerdoodle general
1
Does any body have a good example OR zynq documentation on video out for the snickerdoodle. (VHDL or Verilog)
Have found information on AXI bandwidth and bus transfer types. (Single data..Burst...Stream)
Some questions.I still have.
DDR Memory partitioning between PS (Arm ) and PL (FPGA Logic)?
How this effects the memory map on the Arm side.
And how to implement VDMA to HDMI.
.
It seems a little more complicated than setting up a VGA frame buffer on my Cyclone III Development board?

I realize I could setup a board with separate Static Ram Chip and vga circuit and port my current verilog to the snickerdoodle black.
But I was planning on doing this only if the PiSmasher is not release this year..

P.S. Thanks Ryan I have reicenved my Snickerdoodle black and breakout board.

P.P.S too bad the HDMI2 can not be used as a 2nd HDMI output.
You could then have One Hdmi dedicated to The PS side, And the other dedicated to the PL side.
Although I am sure someone will come up with a PL window inside a PS window.. That would be impressive

Sorry for this long rant
Cheers all

2
The snickerdoodle uses an external chip for HDMI signal transmission, so instead of HDMI you'll need to implement data transmission to that chip. That interface is a lot easier than using HDMI directly, but you won't find an example for this since it is a dedicated interface.

Assuming that the component hasn't changed with the latest piSmasher it is as simple as HSync, Vsync, Active Video + parallel RGB. (like VGA output with the data mapping that you can find in the datasheet).

I do not recommend you implementing HDMI on the PS since it doesn't have HDMI periferals. You'd implement it with bit-banging and performance would be increadibly low. What do you mean by 'window'?

Am Sonntag, 19. November 2017 16:39:21 UTC+1 schrieb Vladmaster99:
Does any body have a good example OR zynq documentation on video out for the snickerdoodle. (VHDL or Verilog)
Have found information on AXI bandwidth and bus transfer types. (Single data..Burst...Stream)
Some questions.I still have.
DDR Memory partitioning between PS (Arm ) and PL (FPGA Logic)?
How this effects the memory map on the Arm side.
And how to implement VDMA to HDMI.
.
It seems a little more complicated than setting up a VGA frame buffer on my Cyclone III Development board?

I realize I could setup a board with separate Static Ram Chip and vga circuit and port my current verilog to the snickerdoodle black.
But I was planning on doing this only if the PiSmasher is not release this year..

P.S. Thanks Ryan I have reicenved my Snickerdoodle black and breakout board.

P.P.S too bad the HDMI2 can not be used as a 2nd HDMI output.
You could then have One Hdmi dedicated to The PS side, And the other dedicated to the PL side.
Although I am sure someone will come up with a PL window inside a PS window.. That would be impressive

Sorry for this long rant
Cheers all

3
1. DDR memory partitioning ... : use HP ports for data transmission PL <-> PS
2. for memory mapping use the Address Editor. address range must be big enough for frame buffer (assuming you want to use VDMA)
3. i recommend the AXI stream to video IP from Xilinx. You can connect it between VDMA output and your custom logic. This way you don't need to worry about AXI anymore
4

Although I am sure someone will come up with a PL window inside a PS window.. That would be impressive

Ok, I think you mean data processing on both PL and PS. If you want a PS window inside a PL window it is actually a simple task (Xilinx already did the hard stuff here). The VDMA is nothing more than a fancy memory controller. You can access the memory on the PL. The PS has its own memory controller and can access the address range as well (this is very high-level, for a better explanation read the docs). For a PL window inside a PS window I guess you can use 2 VDMA's for that, although it would be more efficient to use memory mapped axi interfaces directly.
5

Ok, I think you mean data processing on both PL and PS. If you want a PS window inside a PL window it is actually a simple task.

but before you reach for that, expect some struggeling. For instance, the example design for the VDMA is pretty sh**y. The simulation is set up for 1080p frames and I only have an 8 core Intel I7. I'd take weeks to run the simulation! C'mon Xilinx, what are you doing??
6
Thanks markus for you help