Help needed on FPGA part of the snickerdoodle

snickerdoodle general
1
I have problems using the FPGA part of the snickerdoodle LE. I have created a block design (using the right board files), which implements the zynq and two AXI GPIO IPs.
Creating the bitstream is no problem. I have used pins from JA1 and JA2 as GPIOs.
After exporting the bitstream to the SDK and after writing a small HelloWorld program which is expected to switch the GPIO outputs, I am not able to see the GPIOs changing their output level.

The project is available on github.com (https://github.com/HenryLeinen/SevenSegmentsTest).

Is there someone who can help me with this ? What am I doing wrong here ?
Many thanks.
Henry
2
looks ok to me. Are you aware there's no delay between 'Setting output' and 'Swapping output'?

you might want to add a breakpoint to observe pins changing states.


3
also, which voltage level are you providing on VCCO_35?
4
Well thanks Markus, that was the right question. I guess it does not work with 0V on VCCO_35 !

It works perfectly now :-)


Am Montag, 18. Dezember 2017 00:39:52 UTC+1 schrieb Markus .Markus:
also, which voltage level are you providing on VCCO_35?