How to change boot mode?

snickerdoodle getting-started
1
I've been programming my Snickerdoodle using JTAG interface which is fine for programming the PL, but unfortunately I haven't been able program the PS via XSDK. When I try to I'm met with this error:

Error while launching program:
Memory write error at 0x100000. APB AP transaction error, DAP status f0000021

I've done a little Googling and found that the problem is caused by the boot sequence being set to something other than JTAG. I had a look at the Snickerdoodle manual and found that the boot sequence is determined by MIO pins 4 & 5. Referencing the board schematics, I see that these pins are connected to the QSPI module. How can I go about changing the boot mode so I can actually run code on the Zynq?


2
Hi,

This is something I've run into also during bare metal development in XSDK using XSCT. Can you point to where you have found the information that it is boot source dependent? The default boot source on MIO4/5 is set to SDCard.

I found that it's a "bug" that seems to occur with the Xilinx tools when you have code running actively on the ARM but you are trying to write memory via the JTAG.
If you issue a system reset to the JTAG via the XSCT console then magically the ARM can program. Note that from the message it seems to have something to with the AXI to APB bridge that the Coresight JTAG interface hangs off of.

On the other hand if you are running the debugger in XSDK via JTAG and you halt the ARM processor (or it is executing a WFI/WFE instruction) then there will be no problem writing to memory with the JTAG in my experience.
It's a bit annoying but I have not found any other way around it.

There is a way to change the boot sequence with the buttons or loading alternate firmware and Bush can chime in on that as I believe we have posted files/instructions somewhere for that.


-Jamil


On Saturday, September 30, 2017 at 1:02:47 AM UTC-7, isl...@gmail.com wrote:
I've been programming my Snickerdoodle using JTAG interface which is fine for programming the PL, but unfortunately I haven't been able program the PS via XSDK. When I try to I'm met with this error:

Error while launching program:
Memory write error at 0x100000. APB AP transaction error, DAP status f0000021

I've done a little Googling and found that the problem is caused by the boot sequence being set to something other than JTAG. I had a look at the Snickerdoodle manual and found that the boot sequence is determined by MIO pins 4 & 5. Referencing the board schematics, I see that these pins are connected to the QSPI module. How can I go about changing the boot mode so I can actually run code on the Zynq?


3
I haven't encountered that particular error. While the bootROM sequence and logic is closed-source, I was under the impression that the Zynq would start JTAG mode if the specified default boot source was unavailable (in this case SD card). You can change the boot source by holding down the SELECT button while powering on the snickerdoodle. You will see all of the LEDs on the board turn on for 3 seconds and turn off when the boot sequence has ended. You can release the SELECT button after the LEDs turn off. The platform controller will "remember" the boot selection until the power has been cycled. If you need to reset the Zynq to clear your programming and bitstream, you can press and hold the RESET button for 3 seconds. The APP LED will flash at 1Hz when the reset has been asserted and can then be released. The boot source that was selected during the initial power up will be used when the reset is released. Let me know if this is unclear or if this does/doesn't solve the problem you are encountering.

On Saturday, September 30, 2017 at 7:29:54 AM UTC-7, weath...@krtkl.com wrote:
Hi,

This is something I've run into also during bare metal development in XSDK using XSCT. Can you point to where you have found the information that it is boot source dependent? The default boot source on MIO4/5 is set to SDCard.

I found that it's a "bug" that seems to occur with the Xilinx tools when you have code running actively on the ARM but you are trying to write memory via the JTAG.
If you issue a system reset to the JTAG via the XSCT console then magically the ARM can program. Note that from the message it seems to have something to with the AXI to APB bridge that the Coresight JTAG interface hangs off of.

On the other hand if you are running the debugger in XSDK via JTAG and you halt the ARM processor (or it is executing a WFI/WFE instruction) then there will be no problem writing to memory with the JTAG in my experience.
It's a bit annoying but I have not found any other way around it.

There is a way to change the boot sequence with the buttons or loading alternate firmware and Bush can chime in on that as I believe we have posted files/instructions somewhere for that.


-Jamil


On Saturday, September 30, 2017 at 1:02:47 AM UTC-7, isl...@gmail.com wrote:
I've been programming my Snickerdoodle using JTAG interface which is fine for programming the PL, but unfortunately I haven't been able program the PS via XSDK. When I try to I'm met with this error:

Error while launching program:
Memory write error at 0x100000. APB AP transaction error, DAP status f0000021

I've done a little Googling and found that the problem is caused by the boot sequence being set to something other than JTAG. I had a look at the Snickerdoodle manual and found that the boot sequence is determined by MIO pins 4 & 5. Referencing the board schematics, I see that these pins are connected to the QSPI module. How can I go about changing the boot mode so I can actually run code on the Zynq?


4
The reference for the boot mode solution is here: https://forum.digilentinc.com/topic/3849-problem-running-basic-arty-z7-example/ I tried your suggestions (reset via XSCT and using select to change boot mode) but had no luck.

There's also this forum here which suggests it could be due to a misconfigured DDR module: https://forums.xilinx.com/t5/Embedded-Development-Tools/AP-transaction-Error/td-p/369465

Having a look at the DDR config on the Zynq I've found that it's not setup correctly, as seen below. Can anyone please share the correct config?

5
I found the presets.xml with the DDR configurations on Github and have gone through and manually changed my settings to match those there. One setting has eluded me though, "<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>". I can't find the setting that relates to this. So far I still receive the same APB DAP error when trying to write to the PS even with all of the other DDR configurations set. Is there a way I can just upload presets.xml to Vivado?
6
What version of Vivado are you using? The latest tested version with the board files at https://github.com/krtkl/snickerdoodle-board-files if 2017.1.

On Saturday, September 30, 2017 at 11:04:11 PM UTC-7, isl...@gmail.com wrote:
I found the presets.xml with the DDR configurations on Github and have gone through and manually changed my settings to match those there. One setting has eluded me though, "<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>". I can't find the setting that relates to this. So far I still receive the same APB DAP error when trying to write to the PS even with all of the other DDR configurations set. Is there a way I can just upload presets.xml to Vivado?
7
Yes, the board files already have the correct presets. Otherwise you can also open the zynq processing system IP core, click on Presets and apply the configuration.

Am Sonntag, 1. Oktober 2017 08:04:11 UTC+2 schrieb isl...@gmail.com:
I found the presets.xml with the DDR configurations on Github and have gone through and manually changed my settings to match those there. One setting has eluded me though, "<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>". I can't find the setting that relates to this. So far I still receive the same APB DAP error when trying to write to the PS even with all of the other DDR configurations set. Is there a way I can just upload presets.xml to Vivado?
8
I've just got around to tinkering with this again. I converted the presets.xml to a tcl file and I can now load an application via XSDK without issue on 2017.2. Does the UART0 via MIO 50 - 51 appear via JTAG?

Thanks for your help guys

9
The UART0 does not appear on the JTAG as a debug UART. You can set up the JTAG-UART on the DDC, although I'm not sure if that's what you want to accomplish. I found the following post that outlines the process of setting up your XSDK project for JTAG-UART: https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/JTAG-UART-on-Zynq-Howto/td-p/549541

Summary:

1. Change SDK BSP standalone settings for stdin/stdout to "none" (DCC won't work with stdin/stdout and print/xil_printf etc., you will need to regenerate BSP sources)
2. Replace the xil_printf() call in the example with my own dcc_printf()
3. Start GDB session via Debug As -> Launch on Hardware
4. Open JTAG UART server/terminal by executing "jtag_terminal dcc" in the SDK XMD Console

On Saturday, October 7, 2017 at 2:03:09 AM UTC-7, isl...@gmail.com wrote:
I've just got around to tinkering with this again. I converted the presets.xml to a tcl file and I can now load an application via XSDK without issue on 2017.2. Does the UART0 via MIO 50 - 51 appear via JTAG?

Thanks for your help guys