Individual voltage level for each I/O pin?

Under the topic
"What is the voltage range for snickerdoodle’s I/O pins?"
krtkl wrote:

The voltage levels for the FPGA I/O pins are settable to
between 1.2V and 3.3V ....

.... and each can be set to any I/O voltage in the
aforementioned range.

My question is:

Does this mean it is possible to set each I/O pin to
a individual voltage between 1.2 VDC <= 3.3 VDC ???


No, they are grouped into banks. I'd like to learn more about what configurability the snickerdoodle has per-bank or if the voltages are already hardwired in the design.

On Wednesday, April 20, 2016 at 10:14:47 AM UTC-7, HiSun wrote:
Under the topic
"What is the voltage range for snickerdoodle’s I/O pins?"
krtkl wrote:

The voltage levels for the FPGA I/O pins are settable to
between 1.2V and 3.3V ....

.... and each can be set to any I/O voltage in the
aforementioned range.

My question is:

Does this mean it is possible to set each I/O pin to
a individual voltage between 1.2 VDC <= 3.3 VDC ???


The snickerdoodle has 2 independent FPGA I/O banks with a selectable voltage reference and we provide a 3.3V supply on each you can loop back or you can supply 1.2V to 3.3V externallly.

The snickerdoodle black has 3 independent FPGA I/O banks.

The processing subsystem I/O is statically set to 1.8V and a 1.8V supply pin is provided on that connector. The capacity is not as large as the 3.3V supply but you could also loop that pin back to the FPGA I/O banks if you wanted 1.8V I/O on one of the FPGA banks.

We don't supply 1.2V or 2.5V anywhere so those would have to be generated externally. For instance you could use the supplied 3.3V and a linear regulator to derive 2.5V if you wanted that. Or you could use a fully independent DC supply and just have the 3.3V supply pin as an enable so as to not backfeed the snickerdoodle I/O when the Zynq is turned off.


On Wednesday, April 20, 2016 at 10:14:47 AM UTC-7, HiSun wrote:
Under the topic
"What is the voltage range for snickerdoodle’s I/O pins?"
krtkl wrote:

The voltage levels for the FPGA I/O pins are settable to
between 1.2V and 3.3V ....

.... and each can be set to any I/O voltage in the
aforementioned range.

My question is:

Does this mean it is possible to set each I/O pin to
a individual voltage between 1.2 VDC <= 3.3 VDC ???