Hello Ryan,
Will you provide a dedicated section on a header wich is connected to the ZYNQ, using length matched 50 Ohms pairs (minimum of 4 pairs) LVDS signals interfacing ?
Hi Patrick,
Each of the 4 or 5 40-pin FPGA I/O headers has 12 100-ohm LVDS pairs on them. These are length matched in groups of 6 pairs which also correspond to a "memory byte group" on the Zynq.
You'd need pretty closely spaced wide tracks to get a 50-ohm differential pair so I'm not sure if that's what you meant?
Each of the 4 or 5 40-pin FPGA I/O headers has 12 100-ohm LVDS pairs on them. These are length matched in groups of 6 pairs which also correspond to a "memory byte group" on the Zynq.
You'd need pretty closely spaced wide tracks to get a 50-ohm differential pair so I'm not sure if that's what you meant?
Hello Ryan,
Agree with the 100 ohm standard termination, basically my question was: Are you implementing standard Board Design Guidelines for LVDS Systems ?
Like on Altera GuideLine: https://www.altera.com/en_US/pdfs/literature/wp/wp_lvdsboard.pdf
The short answer is yes. I took a brief look at the Altera document and these are pretty standard approaches for high-speed differential pairs. Our layout team is very experienced with this and had done a great job on the snickerdoodle. We do have a table of track lengths and so forth if that would be helpful to you. I haven't had it added to the manual yet because there are 2 tracks that don't have the correct matches to the associated byte group which we are fixing now with rev 2.
The FPGA I/O aside from 4 or 5 single ended signals is treated as LVDS I/O for the purpose of routing all around. This is a nice thing about the Xilinx SelectIO on the 7-series over the Altera (in and out LVDS and serializers everywhere)
The FPGA I/O aside from 4 or 5 single ended signals is treated as LVDS I/O for the purpose of routing all around. This is a nice thing about the Xilinx SelectIO on the 7-series over the Altera (in and out LVDS and serializers everywhere)
Hello Ryan,
Just for the record, this is what I was talking about:
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf on page 92
