Trouble Programming PL over JTAG in Vivado running Ubuntu

Hi,

I have the snickerdoodle prime LE, breakout board, and Digilent HS3 JTAG programmer. I followed the following tutorial http://www.craftdrones.com/snickerdoodle-blog-index.html to get an external LED with a 1k ohm resistor blinking on JA1.4 (IO_0_35). I was successfully able to program the PS/PL if I export the bitstream file to SDK, create a standalone Hello World application project, and run as –> launch on hardware. The external LED blinks as expected.

However, I cannot program the PL from Vivado while running the snickerdoodle Ubuntu 16.04 image on my sd card. I see the white LED on the snickerdoodle flashing after writing the bitstream to the snickerdoodle with the hardware manager, but the external LED is not doing anything. The only warning message output from the Tcl console is the following:

"WARNING: [Labtools 27-3361] The debug hub core was not detected.

Resolution:

  1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.

  2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use ‘get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]’.

For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908)."

 

Any suggestions as to what I should try? This page of the tutorial http://www.craftdrones.com/blog/program-snickerdoodle-via-jtag mentions something about the FPGA clock not starting. I have a system.bit file on the SD card, but do I need to modify one of the other files on the SD card?

Hello,

Based on the error message, it sounds like there might be an issue with your clock configuration. Can you confirm your FCLK is running and connected?

From the CraftDrones ‘blinky’ tutorial:

Now that the DDR and fixed inputs/outputs are setup, connect the FCLK_CLK0 to the M_AXI_GPIO_ACLK port. This is somewhat confusing but it is basically connecting up the AXI system to the clock.
-Ryan

That was the issue. Thank you for pointing me in the right direction.