Vivado 2017.1?

snickerdoodle general
1
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

2
We haven't tried this yet but I plan on updating next week due to a few other bug fixes in the Xilinx tools.
I will post my experiences if the update is successful.

On Monday, April 24, 2017 at 11:03:43 AM UTC-7, an...@teknikportfoljen.se wrote:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

3
Hi
I have tried it but I faced some problem with vivado 2017.1.
after generate bitstream the vivado cannot open implemented design but the bitstream is completed.
note I ran it on ubuntu 16.4.02

Yours
Mohammed

On Monday, 24 April 2017 19:03:43 UTC+1, an...@teknikportfoljen.se wrote:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

4
I have now found time to test and I got it to work out of the box with Vivado 2017.1. I am running on Windows 10.

I created a simple test project (zynq7 ps + a custom AXI lite peripheral) and I was able to generate the bit file without problem.

I then created a simple standalone Hello World application project in SDK and was able to debug this application via my jtag. I configured the fpga via the "Program FPGA" (also using the jtag).

Reading and writing the registers in the AXI peripheral worked fine...

I have one question though. When I programmed the FPGA via jtag the white LED started to flash (one short fading flash followed by a long fading flash). Why is that?


Den måndag 24 april 2017 kl. 20:03:43 UTC+2 skrev an...@teknikportfoljen.se:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

5
Great to hear, Andreas! The pulsing white LED you see indicates a bitstream has been loaded to your snickerdoodle, so you're seeing the correct behavior.

-Ryan

On Wednesday, May 3, 2017 at 3:52:55 PM UTC-7, andax@teknikportfoljen.se wrote:
I have now found time to test and I got it to work out of the box with Vivado 2017.1. I am running on Windows 10.

I created a simple test project (zynq7 ps + a custom AXI lite peripheral) and I was able to generate the bit file without problem.

I then created a simple standalone Hello World application project in SDK and was able to debug this application via my jtag. I configured the fpga via the "Program FPGA" (also using the jtag).

Reading and writing the registers in the AXI peripheral worked fine...

I have one question though. When I programmed the FPGA via jtag the white LED started to flash (one short fading flash followed by a long fading flash). Why is that?


Den måndag 24 april 2017 kl. 20:03:43 UTC+2 skrev an...@teknikportfoljen.se:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

6
Ryan, Is there more documentation on the LED behaviors? I only found a very short listing of the LEDS, where white was for applications.
After the FPGA has been configured, is there a way I can turn off the white light? To be frank it is somehow a bit annoying to have it constantly flashing! :-)

Best regards,
Andreas

Den torsdag 4 maj 2017 kl. 01:21:51 UTC+2 skrev Cousins:
Great to hear, Andreas! The pulsing white LED you see indicates a bitstream has been loaded to your snickerdoodle, so you're seeing the correct behavior.

-Ryan

On Wednesday, May 3, 2017 at 3:52:55 PM UTC-7, an...@teknikportfoljen.se wrote:
I have now found time to test and I got it to work out of the box with Vivado 2017.1. I am running on Windows 10.

I created a simple test project (zynq7 ps + a custom AXI lite peripheral) and I was able to generate the bit file without problem.

I then created a simple standalone Hello World application project in SDK and was able to debug this application via my jtag. I configured the fpga via the "Program FPGA" (also using the jtag).

Reading and writing the registers in the AXI peripheral worked fine...

I have one question though. When I programmed the FPGA via jtag the white LED started to flash (one short fading flash followed by a long fading flash). Why is that?


Den måndag 24 april 2017 kl. 20:03:43 UTC+2 skrev an...@teknikportfoljen.se:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

7
I found that a very small piece of black electrical tape did the trick!

On Wednesday, May 3, 2017 at 8:29:18 PM UTC-4, an...@teknikportfoljen.se wrote:
Ryan, Is there more documentation on the LED behaviors? I only found a very short listing of the LEDS, where white was for applications.
After the FPGA has been configured, is there a way I can turn off the white light? To be frank it is somehow a bit annoying to have it constantly flashing! :-)
8
Once we finally get around to posting the STM32 code, you'll be able to configure the LEDs however you'd like... :)

On Wednesday, May 3, 2017 at 5:29:18 PM UTC-7, andax@teknikportfoljen.se wrote:
Ryan, Is there more documentation on the LED behaviors? I only found a very short listing of the LEDS, where white was for applications.
After the FPGA has been configured, is there a way I can turn off the white light? To be frank it is somehow a bit annoying to have it constantly flashing! :-)

Best regards,
Andreas

Den torsdag 4 maj 2017 kl. 01:21:51 UTC+2 skrev Cousins:
Great to hear, Andreas! The pulsing white LED you see indicates a bitstream has been loaded to your snickerdoodle, so you're seeing the correct behavior.

-Ryan

On Wednesday, May 3, 2017 at 3:52:55 PM UTC-7, an...@teknikportfoljen.se wrote:
I have now found time to test and I got it to work out of the box with Vivado 2017.1. I am running on Windows 10.

I created a simple test project (zynq7 ps + a custom AXI lite peripheral) and I was able to generate the bit file without problem.

I then created a simple standalone Hello World application project in SDK and was able to debug this application via my jtag. I configured the fpga via the "Program FPGA" (also using the jtag).

Reading and writing the registers in the AXI peripheral worked fine...

I have one question though. When I programmed the FPGA via jtag the white LED started to flash (one short fading flash followed by a long fading flash). Why is that?


Den måndag 24 april 2017 kl. 20:03:43 UTC+2 skrev an...@teknikportfoljen.se:
Hi,

Anyone tried Vivado 2017.1 with Snickerdoodle? Has anyone an idea on the effort or what needs to be updated in the board files etc to run the synthesis/bitstream-generation under the new Vivado 2017.1? The reason I ask is that I have problem running Vivado 2016.x on a computer with 4k screen (a known limitation according to Xilinx), and that is supposed to be fixed since they have updated the GUI quite bit in 2017.1.

Best regards,
Andreas

9
just my two cents. Actually now I'm pretty happy that the led is blinking and the color is white.

I'm not paying attention to the blinking any longer but if it stops, I notice it immediately: the fpga is bricked and it's necessary to turn the power off and on again (happens once in a while after doing something wrong with Zynq)

Now my snickerdoodle is inside an enclosure and the top cover is removed during testing. The led is underneath and white color is easier to see.


On Thursday, May 4, 2017 at 2:29:18 AM UTC+2, an...@teknikportfoljen.se wrote:

...
After the FPGA has been configured, is there a way I can turn off the white light? To be frank it is somehow a bit annoying to have it constantly flashing! :-)
...
10
Glad to hear the "sign of life" LED is working as expected. Sounds like you can save the black electrical tape for more pressing matters... :)

-Ryan

On Friday, May 12, 2017 at 4:47:08 AM UTC-7, pato3cs@gmail.com wrote:
just my two cents. Actually now I'm pretty happy that the led is blinking and the color is white.

I'm not paying attention to the blinking any longer but if it stops, I notice it immediately: the fpga is bricked and it's necessary to turn the power off and on again (happens once in a while after doing something wrong with Zynq)

Now my snickerdoodle is inside an enclosure and the top cover is removed during testing. The led is underneath and white color is easier to see.


On Thursday, May 4, 2017 at 2:29:18 AM UTC+2, an...@teknikportfoljen.se wrote:

...
After the FPGA has been configured, is there a way I can turn off the white light? To be frank it is somehow a bit annoying to have it constantly flashing! :-)
...